1. Field of the Invention
Embodiments of the invention relate generally to non-volatile memory devices. More particularly, embodiments of the invention relate to flash memory devices and related high voltage generating circuits.
A claim of priority is made to Korean Patent Application No. 2006-43882 filed on May 16, 2006, the disclosure of which is hereby incorporated by reference.
2. Description of Related Art
Semiconductor memory devices can be roughly divided into volatile memory devices and non-volatile memory devices. In general, volatile memory devices tend to have faster performance than non-volatile memory devices. However, volatile memory devices generally lose stored data when disconnected from an external power source, whereas non-volatile memory devices retain stored data when disconnected from an external power source.
Due to their ability to retain stored data when disconnected from an external power source, non-volatile memory devices are a popular choice for portable electronic devices such as cellular phones, mp3 players, digital cameras, and so on. Examples of non-volatile memory devices include masked read only memory (MROM), programmable read only memory (PROM), erasable and programmable read only memory (EPROM), and electrically erasable and programmable read only memory (EEPROM), to name but a few.
Among non-volatile memory devices, flash memory devices constitute one especially popular form of EEPROM. Flash memory devices are popular, at least in part, due to their relatively high degree of integration, low power consumption, and their ability to withstand physical shock.
In general, flash memory devices can be categorized into different types based on the organization of flash memory cells into different array structures and according to different read/program characteristics. For example, NAND flash memory devices and NOR flash memory devices each have different array structures and different read/program characteristics providing unique tradeoffs and advantages. In particular, NAND flash memory devices tend to have a higher degree of integration, but slower read times, than NOR flash memory devices. Accordingly, NAND flash memory devices are commonly used to provide mass data storage, while NOR flash memory devices are often used to provide storage for data requiring quick access, such as program code.
In NAND flash memory devices, memory cells are typically erased and programmed using Fowler-Nordheim (FN) tunneling. Selected methods for erasing and programming NAND flash memory devices using FN tunneling are disclosed, for example, in U.S. Pat. Nos. 5,473,563 and 5,696,717, entitled “NONVOLATILE SEMICONDUCTOR MEMORY” and “NONVOLATILE INTEGRATED CIRCUIT MEMORY DEVICES HAVING ADJUSTABLE ERASE/PROGRAM THRESHOLD VOLTAGE VERIFICATION CAPABILITY”, respectively.
NAND flash memory devices can be programmed using a variety of different programming techniques. One common technique used to program NAND flash memory devices is called an incremental step pulse programming (ISPP) technique. In the ISPP technique, a program voltage is applied to a control gate of one or more selected memory cells in a NAND flash memory device in successive program loops until the respective threshold voltages of the selected memory cells reach desired magnitudes. In each successive program loop, the magnitude of the program voltage is increased in order to raise the threshold voltages of the selected memory cells. Selected embodiments of the ISPP technique are disclosed, for example, in U.S. Pat. No. 5,642,309, entitled “AUTO-PROGRAM CIRCUIT IN A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE”.
FIG. 1 is a voltage diagram illustrating a change of a program voltage in a NAND flash memory device during a programming operation using the ISPP technique.
Referring to FIG. 1, the NAND flash memory device receives a program command, a program address, and program data for programming a page of selected memory cells. The program data is loaded into a page buffer circuit and the selected memory cells are identified based on the program address. After the program data is loaded into the page buffer, the program data is simultaneously programmed into the selected memory cells.
In general, the program data is programmed into the selected memory cells using a plurality of program loops each comprising a program period “P” and program verification period “V”. In each program period “P”, the program voltage is applied to a word line connected to the selected memory cells, and appropriate program bias voltages are applied to respective bit lines connected to the selected memory cells based on the program data.
FIG. 1 illustrates five (5) program loops including program periods “P1” through “P5” each having a duration “t”, and corresponding program verification periods “V1” through “V5”. During the five program loops, the program voltage is incrementally increased from a magnitude VPGM1 to a magnitude VPGM5. In each successive program loop, the magnitude of the program voltage changes by an increment ΔVPGM.
During each program verification period, the NAND flash memory device performs a verify read operation to determine whether the selected memory cells have reached desired threshold voltages. In the verify read operation, a read verify reference voltage is applied to the word line connected to the selected memory cells and appropriate read bias voltages are applied to respective bit lines connected to the selected memory cells based on the program data. The read verify operation is then able to determine whether the selected memory cells have reached the desired threshold voltages based on the current conduction characteristics of the selected memory cells under these conditions.
In order to successfully program the selected memory cells using the ISPP technique, the NAND flash memory device must be able to accurately control the magnitude of the program voltage. This is especially true when programming memory cells having relatively small read margins, such as multi-level NAND flash memory cells, because where read margins are small, minor fluctuations in the magnitude of the program voltage can produce undesired threshold voltages, or in other words, wrongly programmed memory cells. For example, in the case of programming multi-level NAND flash memory cells, the duration of each program period “P” may be relatively small, and the magnitude of the program voltage may be relatively large compared with the increment ΔVPGM. Accordingly, absent accurate control of the program voltage, undesired variations in the timing and magnitude of the program voltage may exceed acceptable margins for increment ΔVPGM and duration “t”.
For at least the above reasons, it is desirable to develop reliable, accurate, and stable ways of producing a high voltages in semiconductor devices.